The present invention relates to a current driver circuit for high-speed differential transmission.
With the rapid proliferation of consumer equipment including a digital broadcasting TV and a DVD device, there has been increasing need for high-speed data transmission. To respond to the need, high-speed serial data interface standards such as IEEE 1394 and Serial-ATA have been adopted broadly in the market. According to these high-speed serial data interface technologies, data in an LSI is transmitted differentially at a high speed by a current driver circuit and even high-speed data transmitted from outside the LSI is received differentially by a receiver circuit within the LSI via a pair of transmission lines (twist pair cable).
Because such differential transmission performs long-distance transmission by using a pair of transmission lines, an analog circuit is used in most cases for an input/output unit and a 3.3-V CMOS (Complementary Metal Oxide Semiconductor) transistor is used for the analog circuit. The use of the 3.3-V CMOS transistor is inevitable in terms of protecting a device from an external influence such as ESD (Electrostatic Discharge). It is also necessary in performing differential transmission to determine a common mode potential which is an intermediate potential between a differential pair of signals used for the transmission. If different common mode potentials are set at the transmitter and the receiver, however, a potential difference is inevitably produced on both sides so that a current flows into either of the transmitter and the receiver. To prevent this, it is typical for either the transmitter or the receiver to determine the common mode potential. Accordingly, the common mode potential is normally unfixed and allowed to have a specified range in most cases.
FIG. 8 is a structural view of a conventional current driver circuit for performing differential transmission (see, e.g., U.S. Pat. Nos. 5,418,478 and 5,694,060).
As shown in FIG. 8, the current driver circuit 1 comprises: a pMOS current source transistor 2 connected to a power source potential level Vdd′; an nMOS current source transistor 3 connected to a ground level Vss′; and a switch circuit 4 consisting of four switch elements connected between the pMOS current source transistor 2 and the nMOS current source transistor 3. A pair of transmission lines TP′/NTP′ having respective terminal resistors R′ composed of two series circuits are connected to the switch circuit 4.
In the conventional current driver circuit 1, a current flows from the pMOS current source transistor 2 through the terminal resistors R′ connected between the pair of transmission lines TP′/NTP′ via the switch circuit 4 to be drawn into the nMOS current source transistor 3 again via the switch circuit 4. At this time, a current flowing through the terminal resistors R′ of the pair of transmission lines TP′/NTP′ generates an amplitude using a common mode potential Vcm′ as a center potential. The amplitude thus generated, i.e., the direction of the current flowing through the terminal resistors R′ allows the current driver circuit 1 to transmit an output “1” or “0”.
However, since the common mode potential varies from 0.5 V to about 2.5 V in accordance with, e.g., the IEEE 1394 standard or the like, there is a case where the difference between the power source potential level Vdd′ and the common mode potential Vcm′ becomes 0.2 V if the power source potential level Vdd′ is lowered to, e.g., 2.7 V. In such as a case, the pMOS current source transistor 2 of the current driver circuit 1 inevitably enters a non-saturated region so that the lowering of the power source potential level Vdd′ is limited. Since the common mode potential Vcm′ is high, if a voltage impressed on the both ends of the pMOS current source transistor 2 reaches a value lower than the voltage obtained by subtracting the threshold voltage from the gate voltage, it is difficult to design the pMOS current source transistor 2 such that it reaches a saturated region in terms of the size of the transistor.